MC100EP08DTR2G データシートの表示（PDF） - ON Semiconductor

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MC100EP08DTR2G

3.3V / 5V ECL 2-Input Differential XOR/XNOR

ON Semiconductor 

MC10EP08, MC100EP08

D0 1

D0 2

D1 3

8 VCC

7Q

6Q

D1 4

5

VEE

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

Table 1. PIN DESCRIPTION

PIN

FUNCTION

D0, D1, D0, D1

Q, Q

VCC

VEE

EP

ECL Data Inputs

ECL Data Outputs

Positive Supply

Negative Supply

(DFN8 only) Thermal exposed pad

must be connected to a sufficient

thermal conduit. Electrically connect

to the most negative supply (GND) or

leave unconnected, floating open.

Table 2. TRUTH TABLE

D0*

D1* D0** D1** Q

Q

L

L

H

H

L

H

L

H

H

L

H

L

H

L

L

H

H

L

H

H

L

L

L

H

* Pins will default LOW when left open.

** Pins will default to 0.666% of VCC when left open.

Table 3. ATTRIBUTES

Characteristics

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

SOIC−8

TSSOP−8

DFN8

Flammability Rating

Oxygen Index: 28 to 34

Transistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Value

75 kW

37.5 kW

> 4 kV

> 200 V

> 2 kV

Pb Pkg

Pb−Free Pkg

Level 1

Level 1

Level 1

Level 1

Level 3

Level 1

UL 94 V−0 @ 0.125 in

135 Devices

http://onsemi.com

2

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