MAX5712EUTT データシートの表示（PDF） - Maxim Integrated

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MAX5712EUTT

Low-Power, 12-Bit, Rail to Rail Voltage-Output Serial DAC in SOT23

Maxim Integrated 

MAX5712

Low-Power, 12-Bit, Rail to Rail

Voltage-Output Serial DAC in SOT23

Table 1. Serial Interface Mapping

16-BIT SERIAL WORD

MSB

C3 C2 C1 C0 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01

0 000

12-Bit DAC Code

1 1 1 1XXXXXXXXXX0

1 1 1 1XXXXXXXXXX0

1 1 1 1XXXXXXXXXX1

1 1 1 1XXXXXXXXXX1

LSB

D00

MODE

Set and

update DAC

0

Wake-Up

1 Power-Down

0 Power-Down

1 Power-Down

OUTPUT

VOUT = VDD x

CODE/4096

Current DAC

setting (initially 0)

Floating

1kΩ to GND

100kΩ to GND

Shutdown Modes

The MAX5712 includes three software-controlled shut-

down modes that reduce the supply current to below 1μA.

In two of the three shutdown modes, OUT is connected to

GND through a resistor. Table 1 lists the three shutdown

modes of operation.

Applications Information

Device Powered by an

External Reference

The MAX5712 generates an output voltage proportional

to VDD, coupling power supply noise to the output. The

circuit in Figure 2 rejects this power-supply noise by

powering the device directly with a precision voltage refer-

ence, improving overall system accuracy. The MAX6030

(+3V, 75ppm) or the MAX6050 (+5V, 75ppm) precision

voltage references are ideal choices due to the low-power

requirements of the MAX5712. This solution is also useful

when the required full-scale output voltage is less than the

available supply voltages.

IN

OUT

MAX6050

MAX6030

GND

VDD

MAX5712 OUT

GND

Figure 2. MAX5712 Powered By Reference

Digital Inputs and Interface Logic

The 3-wire digital interface for the MAX5712 is compatible

with SPI, QSPI, MICROWIRE, and DSP. The three digital

inputs (CS, DIN, and SCLK) load the digital input serially

into the DAC. All of the digital inputs include Schmitt-

trigger buffers to accept slow-transition interfaces. This

allows optocouplers to interface directly to the MAX5712

without additional external logic. The digital inputs are

compatible with CMOS-logic levels.

Power-Supply Bypassing and Layout

Careful PC board layout is important for optimal system

performance. Keep analog and digital signals separate

to reduce noise injection and digital feedthrough. Use a

ground plane to ensure that the ground return from GND

to the supply ground is short and low impedance. Bypass

VDD with a 0.1μF capacitor to ground as close as possible

to the device.

Pin Configuration

TOP VIEW

VDD 1

GND 2

MAX5712

6 OUT

5 CS

DIN 3

4 SCLK

SOT23

Chip Information

PROCESS: BiCMOS

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