ML6431 データシートの表示（PDF） - Micro Linear Corporation

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ML6431

Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA

Micro Linear Corporation 

FUNCTIONAL DESCRIPTION

DUAL PLLS

The Genlock has the following properties:

• A stable, asynchronous crystal controlled oscillator

provides the basic timing signals.

• A precision analog circuit uses the above timing

signals to generate an arbitrarily phased output whose

phase can be altered at pixel rate.

• A digital PLL loop monitors the error signal from a

digital phase detector, and generates a pixel by pixel

phase adjustment of the output.

• An intelligent state machine further enhances

performance by monitoring errors and error history and

adjusting the gains of the loop accordingly.

• A circuit automatically detects a VCR signal and

increases loop gain for proper tracking and minimum

jitter.

The digital PLL has five operating modes. In normal

operation with a stable input the controller will settle to

state 1. If errors are large and consistent, controller will

move to state 5. If error conditions are corrected,

controller will sequentially decrease the state as the errors

are reduced toward 0. If small but consistent errors persist

while controller is in state 1, then controller may move to

states 2 or 3 to help settle out errors more quickly. None

of these changes will cause a reset of pixel count, or a

discontinuity of output clocks. Operating modes are

described in greater detail below.

1. Normal: Gain is low, instantaneous phase gain is

1/32, giving a net short term jitter gain (output/input

jitter) of about -30db. Full peak to peak jitter (including

lower frequency jitter) from a white source is about -

15db.

2. Slow: Gain is increased by 4x, and settling time

reduced by about the same. This mode is used as a

transition mode during normal lock sequence, or as a

modest speed up mode if errors are high.

3. Medium: Gain is increased by 8x, and settling time

reduced by about the same. This mode is used as a

transition mode during normal lock sequence, or as a

speed up mode if errors are consistently high.

4. Fast: Gain is increased by 16x. Adds frequency

adjustments to mode 5 for fast settling during hot

switches or pathological gyro errors in hand held

camcorders.

5. Phase: Only Gain is 16x for phase changes, 0 for

frequency changes. Primarily used to quickly settle

head switch phase errors without affecting loop

frequency.

LOW POWER SLEEP MODES

Sleep mode may be initiated either from the serial control

bus, or from an external pin. In both cases the entire chip

except the serial bus is shut down. For applications where

PHERROUT is used, the sleep mode can only be enabled/

disabled via serial control.

ML6430/ML6431

PHERROUT SIGNAL

The PHERROUT pin indicates, on a line by line basis,

whether the H SYNC pulse of the analog input signal is

leading or trailing the genlock's output H SYNC pulse.

This information is used by the genlock to decide whether

to speed up or slow down the internal clock to achieve

locking of the H SYNC pulses. If PHERROUT = 0, then

the analog sync is ahead; therefore, the internal clock

will speed up in an effort to lock the H SYNC pulses. By

contrast, if PHERROUT = 1, then the analog sync is

behind; therefore, the internal clock will slow down in an

effort to lock the H SYNC pulses. Ultimately, when the

genlock is locked to the incoming analog signal,

PHERROUT will alternate approximately every line

between 0 and 1.

PHERROUT (PIN 16)

0

1

DESCRIPTION

Speed up output timing

Slow down output timing

Table 3. PHERROUT Signal Description

SYNC SEPARATION

Sync separation is accomplished using peak tracking

analog amplifiers with a precision sync slicer. The closed

tracking loop is equipped with timers to discriminate true

sync pulses from noise glitches or chroma overshoots. The

use of analog sync separation techniques removes a

serious source of jitter present in most digital PLLs.

CRYSTAL SELECTION

The precision crystal source for the ML6430/ML6431 can

be supplied in one of four ways. An industry standard

3.58MHz parallel tuned NTSC color subcarrier crystal or a

4.43MHz parallel tuned PAL color subcarrier crystal may

be used. Alternately, a 14.318MHz NTSC or 17.7MHz

PAL, 4xFs, or a 3.58MHz or 4.43MHz oscillator source

may be used. Regardless of the crystal used, the ML6430/

ML6431 can lock to PAL, NTSC, Beta or MII or YUV in

either 625 or 525 standards. Table 4 provides the clock

rate accuracy for both the NTSC and PAL clock rates for

each crystal selected. Note that the range may vary

between the ML6430 and the ML6431.

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