IP1201PBF データシートの表示（PDF） - International Rectifier

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IP1201PBF

Dual Output Full Function 2 Phase Synchronous Buck Power Block

International Rectifier 

iP1201PbF

Pin Name

VIN

Ball Designator

A1 A2 A3 A4 A5 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5

B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C14 C15 C16

C17 C18

A*

G8 J13

B*

CC1

CC2

L12 L13

H8

H13

Pin Description

Input voltage connection node

Internally generated voltage. Connect to pin B when Vin < 3.5V.

Leave floating for input voltages >3.5V. Externally, add a 2.2µF

capacitor

Internally generated voltage. Connect to pin A when Vin < 3.5V.

Leave floating for input voltages >3.5V. Externally, add a 2.2µF

capacitor

Output of the first error amplifier, refer to Fig.1 block diagram

Output of the second error amplifier

ENABLE

A8 B8

Single pin for both outputs. Commands outputs ON or OFF. Pulled

low, turns both outputs ON. Should be pulled high to disable outputs.

SS1

SS2

FB1

FB1s

FB2

FB2s

VSW1

VSW2

PGND

Vref

VP-ref

SYNC

RT

PGOOD

HICCUP

NC

H6

Soft start pin for output1. External capacitor

provides soft start. Pulled low disables output 1.

G11

Soft start pin for output2. External capacitor

provides soft start. Pulled low disables output 2.

J6

Inverting input of error amplifier 1

J8

Output 1 voltage sense pin

H11

Inverting input of error amplifier 2

J11

Output 2 voltage sense pin

D1 D2 D3 E1 E2 F1 F2 G1 G2 G3 H1 H2 H3 J1 J2 J3 K1

K2 L1 L2

Output 1 inductor connection node

D16 D17 D18 E17 E18 F17 F18 G16 G17 G18 H16 H17

H18 J16 J17 J18 K17 K18 L17 L18

Output 2 inductor connection node

A6 A7 A9 A10 A12 A13 B6 B7 B9 B10 B12 B13 C6 C7 C9

C10 C12 C13 D6 D7 D9 D10 D12 D13 D14 E3 E4 E8 E11

E15 E16 F3 F4 F5 F6 F9 F10 F13 F14 F15 F16 G4 G5 G6

Power Ground

G9 G10 G13 G14 G15 H4 H5 H9 H10 H14 H15 J4 J5 J9

J10 J14 J15 K3 K16 L3 L5 L14 L16

L9

Amplifier 1 reference Voltage. Connect a 100pf cap from this pin to

PGND.

Amplifier 2 reference voltage. Connect to Vref for independent

L8

output configuration. Refer to function description section on how to

connect for parallel configuration.

K6

External Clock synchronization pin. Set free running frequency to

80% of the SYNC frequency. When not in use leave pin floating.

K13

Switching frequency setting pin. For RT selection, refer to Fig.11 RT

vs Frequency curve.

L10

L6 L7

L11

Power Good pin, needs external pull-up resistor. If not used pin can

be left floating.

Logic level pin. Pulled high enables hiccup mode of operation. Pulled

low enables overcurrent shutdown mode.

Unused pin. No electrical connection.

* Part will malfunction if pins A and B are shorted together for input voltages >3.5V

Table 1: Pin Description

10

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