PM4354 データシートの表示（PDF） - PMC-Sierra

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PM4354

FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER/FRAMER

PMC-Sierra 

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

8

PIN DESCRIPTION

By convention, where a bus of four pins is present, the index indicates to which quadrant the pin

applies. With BRCLK[1:4], for example, BRCLK[1] applies to quadrant #1, BRCLK[2] applies to

quadrant #2, BRCLK[3] applies to quadrant #3, and BRCLK[4] applies to quadrant #4.

Pin Name Type Pin No. Function

T1 and E1 System Side Serial Clock and Data Interface

BRCLK[1] I/O

BRCLK[2]

BRCLK[3]

BRCLK[4]

E2 Backplane Receive Clocks (BRCLK[1:4]). The Backplane Receive Clock,

F16 BRCLK[x], is used to update BRPCM[x] and BRSIG[x] and to either update or

N1 sample BRFP[x], depending on the direction of BRFP[x]. The active edge of

N16 BRCLK[x] for sampling/updating BRPCM[x], BRSIG[x], and BRFP[x] is

configurable.

In Receive Clock Master Mode, BRCLK[x] is configured as an output and can

be either a 1.544 MHz or 2.048 MHz clock derived from the recovered line

rate timing, with optional jitter attenuation.

When in Receive Clock Master: Nx64Kbit/s mode, BRCLK[x] is gapped

during the framing bit position (T1 mode only) and optionally for between 1

and 24 DS0 channels or 1 and 32 timeslots in the associated BRPCM[x]

stream.

When in Receive Clock Slave: Full T1/E1 mode, BRCLK[x] is configured as

an input and is either a 1.544MHz clock in T1 mode or a 2.048MHz clock in

T1 or E1 modes. BRCLK[x] is a nominal 1.544 or 2.048 MHz clock +/-

50ppm with a 50% duty cycle.

When in Receive Clock Slave: H-MVIP mode, BRCLK[x] is configured as an

input and is unused. In this mode, it is recommended that BRCLK[x] be

connected via an external resistor to ground.

After a reset, BRCLK[x] is configured as an input.

BRSIG[1]

BRSIG[2]

BRSIG[3]

BRSIG[4]

Output E3

G15

P2

P16

Backplane Receive Signaling (BRSIG[1:4]). Each BRSIG[x] contains the

extracted channel associated signaling bits for each channel in the frame,

repeated for the entire superframe. Each channel's associated signaling bits

are valid in bit locations 5,6,7,8 of the channel and are channel-aligned with

the BRPCM[x] data stream.

When in Receive Clock Slave: H-MVIP mode, BRSIG[x] is unused and driven

low.

BRSIG[x] is updated on the active edge of BRCLK[x].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

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