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APA3160 データシートの表示（PDF） - Anpec Electronics

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APA3160

Anpec Electronics

APA3160 Datasheet PDF : 44 Pages

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APA3160

Function Description (Cont.)

Shutdown Sequence

Enter:

1. Ensure I2S clocks have been stable and valid for at least 50ms.

2. Write 0x40 to register 0x05.

3. Wait at least 1ms+1.3xt (where t is specified by register 0x1A).

stop

4. Once in shutdown, stable clocks are not required while device remains idle.

5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step

4 of initialization sequence.

Exit:

1. Ensure I2S clocks have been stable and valid for at least 50ms.

2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms after trim following

AVDD/DVDD powerup ramp).

3. Wait at least 1ms+1.3xtstart (where tstart is specified by register 0x1A).

4. Proceed with normal operation.

Power-down Sequence

Use the following sequence to power-down the device and its supplies:

1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert SD=0 and

wait at least 2ms.

2. Assert RST=0.

3. Drive digital inputs low and ramp down PVDD supply as follows:

• Drive all digital inputs low after RST has been low for at least 2µs.

• Ramp down PVDD while ensuring that it remains above 8V until RST has been low for at least 2µs.

4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and that it is never more

than 2.5V below the digital inputs.

Table 1. Serial Control Interface Register Summary

Sub Address

No. of Bytes

Contents

A u indicates unused bits.

0x00

Clock control register