APA3160 データシートの表示（PDF） - Anpec Electronics

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APA3160

20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC

Anpec Electronics 

APA3160

Function Description (Cont.)

Recommended Use Model (Cont.)

Parameter

Description

APA3160

Min. Typ. Max.

tVDDH-DL Time digital inputs must remain low after AVDD/DVDD goes above 3V

0

-

-

tDL-VDDH Time digital inputs must be low before AVDD/DVDD goes below 3V

0

-

-

tVDDH-PVDDL Time PVDD/AVCC remains below 7.5V after AVDD/DVDD goes above 3V

100

-

-

tPVDDL-VDDH Time PVDD/AVCC must be below 7.5V before AVDD/DVDD goes below 3V

0

-

-

tPVDDH-I2C Time PVDD/AVCC must be above 10V before I2C commands may address device 10

-

-

tRL-PVDDH Time PVDD/AVCC must remain above 10V after RST goes low

tRH-I2C Time RESET must be high before I2C commands may address device

2

-

-

13.5

-

-

tDV-RH Time digital inputs must be valid (driven as recommended) before RST goes high 100

-

-

tRL-DV Time digital inputs must remain valid (driven as recommended) after RST goes low 2

-

-

tautodetect

Auto-detect completion wait time (given stable and valid clocks) before issuing

further commands

50

-

-

texitSD

Exit shutdown wait time before issuing further commands to device (t start given by 1+1.3 x

register 0x1A)

tstart

-

-

tenterSD

Enter shutdown wait time before issuing further commands to device (t stop given 1+1.3 x

by register 0x1A)

tstop

-

-

tPOR

Power-on-reset wait time after 1st trim following AVDD/DVDD power-up (tstart given 240 +

by register 0x1A) (does not apply to trim commands following subsequent resets) 1.3 x tstart

-

-

Unit

µs

ms

µs

ms

Sudden Power Loss (BD)

AVDD/DVDD

SD

3V

tDL-VDDH

MCLK

I2S

LRCLK

SCLK

SDIN

I2C

SCL

SDA

tPL-HL

RST

PVDD/AVCC

tRL-PVCCH

10V

7.5V

tPVCCL-VDDH

Figure 22. Power Loss Sequence

Copyright © ANPEC Electronics Corp.

21

Rev. A.4 - Jan., 2013

www.anpec.com.tw

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