DS83C520-QCL(2000) データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS83C520-QCL Datasheet PDF : 42 Pages
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EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
SYMBOL MIN
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
tCHCX
10
tCLCX
10
tCLCL
tCHCL
TYP
DS87C520/DS83C520
MAX
5
5
UNITS
ns
ns
ns
ns
NOTES
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER
SYMBOL MIN
TYP
Serial Port Clock Cycle Time
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Output Data Setup to Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Output Data Hold from Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Input Data Hold after Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Clock Rising Edge to Input Data
Valid
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
12tCLCL
4tCLCL
10tCLCL
3tCLCL
2tCLCL
tCLCL
tCLCL
tCLCL
11tCLCL
3tCLCL
MAX
UNITS
ns
ns
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following is an explanation of the
symbols.
t
Time
A Address
C Clock
D Input data
H Logic level high
L Logic level low
I
Instruction
P
PSEN
Q Output data
R
RD signal
V Valid
W WR signal
X No longer a valid logic level
Z Tristate
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