ADUM1100 データシートの表示（PDF） - Analog Devices
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ADUM1100 Datasheet PDF : 20 Pages
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Data Sheet
ADuM1100
Parameter
Symbol Min
Pulse Width Distortion, |tPLH − tPHL|5
PWD
5 V/3 V Operation
3 V/5 V Operation
Change in Pulse Width Distortion vs.
Temperature6
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal
tPSK1
Temperature)5, 7
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal
tPSK2
Temperature, Supplies)5, 7
5 V/3 V Operation
3 V/5 V Operation
Output Rise/Fall Time (10% to 90%)
tR, tF
Common-Mode Transient Immunity at |CML|,
25
Logic Low/High Output8
|CMH|
Refresh Rate
fr
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current9
CPD1
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current9
CPD2
5 V/3 V Operation
3 V/5 V Operation
Typ Max Unit
0.5
2
ns
0.5
3
ns
Test Conditions
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
3
ps/°C
CL = 15 pF, CMOS signal levels
10
ps/°C
CL = 15 pF, CMOS signal levels
12 ns
15 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
9
12
3
35
1.2
1.1
0.09
0.08
0.04
0.02
ns
ns
ns
kV/μs
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VI = 0 V or VDD1, VCM = 1000 V,
transient magnitude = 800 V
Mbps
Mbps
mA/Mbps
mA/Mbps
mA/Mbps
mA/Mbps
1 Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the
rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width
distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the
impact of given input rise/fall times on these parameters.
6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the
recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
Rev. I | Page 9 of 20
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