74LVQ573SJX(1998) データシートの表示（PDF） - Fairchild Semiconductor

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74LVQ573SJX
(Rev.:1998)

Low Voltage Octal Latch with 3-STATE Outputs

Fairchild Semiconductor 

Truth Table

Inputs

Outputs

OE

LE

D

On

L

H

H

H

L

H

L

L

L

L

X

O0

H

X

X

Z

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immaterial

O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Logic Diagram

Functional Description

The LVQ573 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is HIGH,

data on the Dn inputs enters the latches. In this condition the

latches are transparent, i.e., a latch output will change state

each time its D-type input changes. When LE is LOW the

latches store the information that was present on the D-type

inputs a setup time preceding the HIGH-to-LOW transition of

LE. The 3-STATE buffers are controlled by the Output En-

able (OE) input. When OE is LOW, the buffers are enabled.

When OE is HIGH the buffers are in the high impedance

mode but this does not interfere with entering new data into

the latches.

DS011361-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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