Philips Semiconductors
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
Product specification
74LVC16373A;
74LVCH16373A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
CI
CPD
propagation delay Dn to Qn
propagation delay LE to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
input capacitance
power dissipation per latch
CONDITIONS
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
VCC = 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
a) PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacity in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
3.0
3.4
3.5
3.9
5.0
15
11
UNIT
ns
ns
ns
ns
pF
pF
pF
ORDERING INFORMATION
TYPE NUMBER
74LVC16373ADGG
74LVCH16373ADGG
74LVC16373ADL
74LVCH16373ADL
TEMPERATURE RANGE
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
PINS
48
48
48
48
PACKAGE
PACKAGE MATERIAL
TSSOP48
TSSOP48
SSOP48
SSOP48
plastic
plastic
plastic
plastic
CODE
SOT362-1
SOT362-1
SOT370-1
SOT370-1
2003 Dec 08
3