AD5222 データシートの表示（PDF） - Analog Devices

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AD5222

Increment/Decrement Dual Digital Potentiometer

Analog Devices 

AD5222

OPERATION

The AD5222 provides a 128-position, digitally-controlled, variable

resistor (VR) device. Changing the VR settings is accomplished

by pulsing the CLK pin while CS is active low. The U/D (UP/

DOWN) control input pin controls the direction of the increment.

When the wiper hits the end of the resistor (Terminal A or B)

additional CLK pulses no longer change the wiper setting. The

wiper position is immediately decoded by the wiper decode logic

changing the wiper resistance. Appropriate debounce circuitry is

required when push-button switches are used to control the

count sequence and direction of count. The exact timing require-

ments are shown in Figure 2. The AD5222 powers ON in a

centered wiper position, exhibiting nearly equal resistances of

RWA and RWB.

VDD AD5222

A1

U/D

UP/DOWN

COUNTER

DECODE

W1

B1

POR

CS

DAC

A2

MODE

DACSEL

SELECT

AND

UP/DOWN

COUNTER

DECODE

W2

CLK

ENABLE

B2

GND

VSS

Figure 29. Block Diagram

DIGITAL INTERFACING OPERATION

The AD5222 contains a push-button controllable interface. The

active inputs are clock (CLK), CS and up/down (U/D). While

the MODE, and DACSEL pins control common updates or

individual updates. The negative-edge sensitive CLK input

requires clean transitions to avoid clocking multiple pulses into

the internal UP/DOWN counter register, Figure 30. Standard

logic families work well. If mechanical switches are used for

product evaluation a flip-flop or other suitable means should

debounce them. When CS is taken active low, the clock begins

to increment or decrement the internal up/down counter, depen-

dent upon the state of the U/D control pin. The UP/DOWN

counter value (D) starts at 40H at system power ON. Each new

CLK pulse will increment the value of the internal counter by

1 LSB until the full-scale value of 7FH is reached, as long as the

U/D pin is logic high. If the U/D pin is taken to logic low, the

counter will count down, stopping at code 00H (zero-scale).

Additional clock pulses on the CLK pin are ignored when the

wiper is at either the 00H position or the 7FH position. The

detailed digital logic interface circuitry is shown in Figure 30.

U/D

DACSEL

MODE

RDAC 1

U/D

COUNTER

CS

CLK

RDAC 2

U/D

COUNTER

Figure 30. Detailed Digital Logic Interface Circuit

All digital inputs (CS, U/D, CLK, MODE, DACSEL) are

protected with a series input resistor and parallel Zener ESD

structure shown in Figure 31. All potentiometer terminal pins

(A, B, W) are protected from ESD as shown in Figure 32.

1k⍀

VSS

LOGIC

Figure 31. Equivalent ESD Protection Digital Pins

20⍀

A, B, W

VSS

Figure 32. Equivalent ESD Protection Analog Pins

RS

A

D0

RS

D1

D2

D3

RS

D4

D5

D6

W

RDAC

UP/DOWN

CNTR

&

DECODE

RS

B

RS = RNOMINAL/128

Figure 33. AD5222 Equivalent RDAC Circuit

–8–

REV. 0

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