ADAU1401AWBSTZ-RL(Rev0) データシートの表示（PDF） - Analog Devices

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ADAU1401AWBSTZ-RL
(Rev.:Rev0)

SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs

Analog Devices 

ADAU1401A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

AGND 1

ADC1 2

ADC_RES 3

ADC0 4

RESET 5

SELFBOOT 6

ADDR0 7

MP4/INPUT_LRCLK 8

MP5/INPUT_BCLK 9

MP1/SDATA_IN1 10

MP0/SDATA_IN0 11

DGND 12

PIN 1

INDICATOR

ADAU1401A

TOP VIEW

(Not to Scale)

36 AVDD

35 PLL_LF

34 PVDD

33 PGND

32 MCLKI

31 OSCO

30 RSVD

29 MP2/SDATA_IN2/AUX_ADC1

28 MP3/SDATA_IN3/AUX_ADC2

27 MP8/SDATA_OUT2/AUX_ADC3

26 MP9/SDATA_OUT3/AUX_ADC0

25 DGND

13 14 15 16 17 18 19 20 21 22 23 24

Figure 7. 48-Lead LQFP Pin Configuration

Table 11. Pin Function Descriptions

Pin No. Mnemonic

Type 1

1, 37, 42 AGND

PWR

2

ADC1

A_IN

3

ADC_RES

4

ADC0

5

RESET

A_IN

A_IN

D_IN

6

SELFBOOT

D_IN

7

ADDR0

D_IN

8

9

10

11

12, 25

13, 24

MP4/INPUT_LRCLK

MP5/INPUT_BCLK

MP1/SDATA_IN1

MP0/SDATA_IN0

DGND

DVDD

D_IO

D_IO

D_IO

D_IO

PWR

PWR

Description

Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a

common ground plane. AGND should be decoupled to an AVDD pin with a 100 nF capacitor.

Analog Audio Input 1. Full-scale 100 μA rms input. The current input allows the input voltage

level to be scaled with an external resistor. An 18 kΩ resistor results in a 2 V rms full-scale input.

See the Audio ADCs section for details.

ADC Reference Current. The full-scale current of the ADCs can be set with an external 18 kΩ

resistor connected between this pin and ground. See the Audio ADCs section for details.

Analog Audio Input 0. Full-scale 100 μA rms input. The current input allows the input voltage

level to be scaled with an external resistor. An 18 kΩ resistor results in a 2 V rms full-scale input.

Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1401A exits

reset on a low-to-high edge. For more information about initialization, see the Power-Up

Sequence section for details.

Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting

this pin high initiates a self-boot operation when the ADAU1401A is brought out of a reset.

This pin can be tied directly to the control voltage or pulled up/down with a resistor. See

the Self-Boot section.

I2C and SPI Address 0. In combination with ADDR1, this pin allows up to four ADAU1401A

devices to be used on the same I2C bus or up to two ICs to be used with a common SPI

CLATCH signal. See the I2C Port section for details.

Multipurpose GPIO/Serial Input Port LRCLK. See the Multipurpose Pins section for more details.

Multipurpose GPIO/Serial Input Port BCLK. See the Multipurpose Pins section for more details.

Multipurpose GPIO/Serial Input Port Data 1. See the Multipurpose Pins section for more details.

Multipurpose GPIO/Serial Input Port Data 0. See the Multipurpose Pins section for more details.

Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a

common ground plane. DGND should be decoupled to a DVDD pin with a 100 nF capacitor.

1.8 V Digital Supply. The input for this pin can be supplied either externally or generated

from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be decoupled to DGND

with a 100 nF capacitor.

Rev. 0 | Page 10 of 10

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