KSC5502DT データシートの表示（PDF） - Fairchild Semiconductor

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KSC5502DT

NPN Triple Diffused Planar Silicon Transistor

Fairchild Semiconductor 

Physical Dimensions

Figure 30. TO-220, MOLDED, 3LEAD, JEDEC VARIATION AB

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/TO/TO220B03.pdf.

For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:

http://www.fairchildsemi.com/packing_dwg/PKG-TO220B03.pdf.

© 2000 Fairchild Semiconductor Corporation

KSC5502D / KSC5502DT Rev. 1.1.0

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