XRT83SL30 データシートの表示（PDF） - Exar Corporation
部品番号
コンポーネント説明
メーカー
XRT83SL30
Exar Corporation
XRT83SL30 Datasheet PDF : 77 Pages
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XRT83SL30
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
CLOCK SYNTHESIZER
SIGNAL NAME
MCLKT1
PIN #
14
TYPE
I
DESCRIPTION
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
NOTES:
1. See MCLKE1 description for further explanation for the usage of
this pin.
2. Internally pulled “Low” with a 50kΩ resistor.
MCLKOUT
16
O Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based on the mode of operation.
CLKSEL2
17
I
Clock Select input for Master Clock Synthesizer pin 2
CLKSEL1
18
Clock Select input for Master Clock Synthesizer pin 1
CLKSEL0
19
Clock Select input for Master Clock Synthesizer pin 0
In Hardware Mode, CLKSEL[2:0] are input signals to a programmable fre-
quency synthesizer that can be used to generate a master clock from an
external accurate clock source according to the following table. The
MCLKRATE control signal is generated from the state of EQC[4:0] inputs.
See Table 5 for description of Transmit Equalizer Control bits.
In Host Mode, the state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits.
MCLKE1 MCLKT1
(kHz)
(kHz)
2048
2048
2048
2048
2048
1544
1544
1544
1544
1544
2048
1544
8
X
8
X
16
X
16
X
56
X
56
X
64
X
64
X
128
X
128
X
256
X
256
X
CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
CLKOUT
(KHz)
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
NOTE: Internally pulled "Low" with a 50kΩ resistor.
10
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