XRT72L50IQ データシートの表示（PDF） - Exar Corporation
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XRT72L50IQ Datasheet PDF : 471 Pages
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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.2.1
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Operation) .................................................................................................................................................... 324
5.3.5.2 Nibble-Parallel Mode Operation Behavior of the XRT72L50 ....................................................... 325
Figure 139. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface block of the
XRT72L50 and the Terminal Equipment ...................................................................................................... 325
Figure 140. The XRT72L50 DS3/E3 Framer IC being interfaced to the Receive Section of the Terminal Equipment (Nibble-
Parallel Mode Operation) ............................................................................................................................. 326
5.3.6 Receive Section Interrupt Processing ................................................................................................... 327
5.3.6.1 Enabling Receive Section Interrupts ........................................................................................... 327
Figure 141. Illustration of the signals that are output via the Receive Payload Data Output Interface block (for Nibble-Parallel
Mode Operation). ......................................................................................................................................... 327
5.3.6.2 Enabling/Disabling and Servicing Interrupts ................................................................................ 328
6.0 E3/ITU-T G.832 Operation of the XRT72L50 ..................................................................................... 339
6.1 DESCRIPTION OF THE E3, ITU-T G.832 FRAMES AND ASSOCIATED OVERHEAD BYTES ........................................ 339
6.1.1 Definition of the Overhead Bytes ........................................................................................................... 339
Figure 142. Illustration of the E3, ITU-T G.832 Framing Format. ................................................................................ 339
6.1.1.1 Frame Alignment (FA1 and FA2) Bytes ...................................................................................... 340
6.1.1.2 Error Monitor (EM) Byte .............................................................................................................. 340
6.1.1.3 The Trail-Trace Buffer (TTB) Byte ............................................................................................... 340
6.1.1.4 Maintenance and Adaptation (MA) Byte ..................................................................................... 341
TABLE 65: DEFINITION OF THE TRAIL TRACE BUFFER BYTES, WITHIN THE E3, ITU-T G.832 FRAMING FORMAT ................. 341
6.1.1.5 The Network Operator (NR) Byte ................................................................................................ 342
6.1.1.6 The General Purpose Communications Channel (GC) Byte ....................................................... 342
6.2 THE TRANSMIT SECTION OF THE XRT72L50 (E3 MODE OPERATION) .................................................................. 342
TABLE 66: A LISTING OF THE VARIOUS PAYLOAD TYPE VALUES AND THEIR CORRESPONDING MEANING ............................. 342
6.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 343
Figure 143. The Transmit Section configured to operate in the E3 Mode ................................................................... 343
Figure 144. The Transmit Payload Data Input Interface Block .................................................................................... 344
TABLE 67: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE ... 344
6.2.1.1 Mode 1 - The Serial/Loop-Timing Mode ...................................................................................... 346
Figure 145. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 1(Serial/
Loop-Timed) Operation ................................................................................................................................ 346
Figure 146. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface block of the
XRT72L50 and the Terminal Equipment (for Mode 1 Operation) ................................................................. 347
6.2.1.2 Mode 2 - The Serial/Local-Timed/Frame-Slave Mode Behavior of the XRT72L50 ..................... 348
Figure 147. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 2 (Serial/
Local-Timed/Frame-Slave) Operation .......................................................................................................... 349
6.2.1.3 Mode 3 - The Serial/Local-Timed/Frame-Master ModeBehavior of the XRT72L50 .................... 350
Figure 148. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (Mode 2
Operation) .................................................................................................................................................... 350
Figure 149. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 3 (Serial/
Local-Timed/Frame-Master) Operation ........................................................................................................ 351
6.2.1.4 Mode 4 - The Nibble-Parallel/Loop-Timed Mode Behavior of the XRT72L50 ............................. 352
Figure 150. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (E3 Mode 3
Operation) .................................................................................................................................................... 352
Figure 151. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 4 (Nibble-
Parallel/Loop-Timed) Operation ................................................................................................................... 353
Figure 152. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (Mode 4
Operation) .................................................................................................................................................... 354
6.2.1.5 Mode 5 - The Nibble-Parallel/Local-Time/Frame-Slave Interface Mode Behavior of the XRT72L50 .
355
Figure 153. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 5 (Nibble-
Parallel/Local-Timed/Frame-Slave) Operation ............................................................................................. 356
6.2.1.6 Mode 6 - The Nibble-Parallel/Local-Timed/Frame-Master Interface Mode Behavior of the XRT72L50
357
Figure 154. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (E3 Mode 5
Operation) .................................................................................................................................................... 357
Figure 155. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 6 (Nibble-
Parallel/Local-Timed/Frame-Master) Operation ........................................................................................... 358
6.2.2 The Transmit Overhead Data Input Interface ........................................................................................ 359
Figure 156. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (E3 Mode 6
Operation) .................................................................................................................................................... 359
Figure 157. The Transmit Overhead Data Input Interface block .................................................................................. 360
TABLE 68: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE XRT72L50 IC
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