SM5852FS データシートの表示（PDF） - Nippon Precision Circuits

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SM5852FS

Digital Dynamic Bass Boost LSI

Nippon Precision Circuits  

INPUT/OUTPUT TIMING

Input Timing

SM5852FS

LRCO

BCKO

DOUT

MSB

Lch

LSB

MSB

Rch

LSB

There must be a minimum of 16 BCKI clock cycles to read in a single word of data.

Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement

format.

Output Timing

LRCO

BCKO

DOUT ,,

MSB

Lch

Shaded areas represent intervals of invalid data.

LS,,B ,,

MSB

Rch

LS,,B ,,

NIPPON PRECISION CIRCUITS—11

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