X1228SG データシートの表示（PDF） - Intersil

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X1228SG

Real Time Clock/Calendar/CPU Supervisor with EEPROM

Intersil 

X1228

Small Outline Package Family (SO)

A

D

N

(N/2)+1

h X 45°

E

E1

PIN #1

I.D. MARK

A

c

SEE DETAIL “X”

1

B

0.010 M C A B

e

C

(N/2)

H

SEATING

PLANE

0.004 C

0.010 M C A B

b

L1

A2

GAUGE

PLANE 0.010

A1

L

4° ±4°

DETAIL X

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

SO-8

SO-14

SO16

(0.150”)

A

0.068

0.068

0.068

A1

0.006

0.006

0.006

A2

0.057

0.057

0.057

b

0.017

0.017

0.017

c

0.009

0.009

0.009

D

0.193

0.341

0.390

E

0.236

0.236

0.236

E1

0.154

0.154

0.154

e

0.050

0.050

0.050

L

0.025

0.025

0.025

L1

0.041

0.041

0.041

h

0.013

0.013

0.013

N

8

14

16

SO16 (0.300”)

(SOL-16)

0.104

0.007

0.092

0.017

0.011

0.406

0.406

0.295

0.050

0.030

0.056

0.020

16

SO20

(SOL-20)

0.104

0.007

0.092

0.017

0.011

0.504

0.406

0.295

0.050

0.030

0.056

0.020

20

SO24

(SOL-24)

0.104

0.007

0.092

0.017

0.011

0.606

0.406

0.295

0.050

0.030

0.056

0.020

24

SO28

(SOL-28)

0.104

0.007

0.092

0.017

0.011

0.704

0.406

0.295

0.050

0.030

0.056

0.020

28

TOLERANCE

MAX

±0.003

±0.002

±0.003

±0.001

±0.004

±0.008

±0.004

Basic

±0.009

Basic

Reference

Reference

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

NOTES

-

-

-

-

-

1, 3

-

2, 3

-

-

-

-

-

Rev. L 2/01

28

FN8100.4

May 18, 2006

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