XWM8739LEFL データシートの表示（PDF） - Wolfson Microelectronics plc
部品番号
コンポーネント説明
メーカー
XWM8739LEFL Datasheet PDF : 35 Pages
| |||
WM8739 / WM8739L
Advanced Information
REGISTER
BIT
ADDRESS
0000101
0
Digital Audio Path
Control
LABEL
ADCHPD
4
HPOR
0000110
Power Down
Control
0
LINEINPD
2
ADCPD
5
OSCPD
7
POWEROFF
0000111
1:0
Digital Audio
Interface Format
FORMAT[1:0]
3:2 IWL[1:0]
4
LRP
0001000
Sampling
Control
6
MS
0
USB/
NORMAL
1
BOSR
5:2 SR[3:0]
6
CLKIDIV2
DEFAULT
DESCRIPTION
0
0
1
1
0
1
10
10
0
0
0
0
0000
(fs)
0
ADC High Pass Filter Enable (Digital)
1 = Disable High Pass Filter
0 = Enable High Pass Filter
Store dc offset when High Pass Filter
disabled
1 = store offset
0 = clear offset
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
ADC Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
POWEROFF mode
1 = Enable POWEROFF
0 = Disable POWEROFF
Audio Data Format Select
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK rising
edge after LRC rising edge
0 = MSB is available on 1st BCLK rising
edge after LRC rising edge
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Mode Select
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
ADC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
AI Rev 2.2 September 2001
28
Share Link: 