W65C02S データシートの表示（PDF） - Unspecified

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W65C02S

8-bit Microprocessor

Unspecified 

The Western Design Center, Inc.

Address Mode

1a. Absolute a

ADC, AND, BIT, CMP, CPX, CPY, EOR,

LDA, LDX, LDY, ORA, SBC, STA, STX,

STY, STZ

16 OpCodes, 3 bytes, 4&5 cycles

1b. Absolute (R-M-W) a

ASL, DEC, INC, LSR, ROL, ROR, TRB,

TSB

8 OpCodes, 3 bytes, 6 cycles

1c. Absolute (JUMP) a

JMP (4C)

1 OpCode, 3 bytes, 3 cycles

1d. Absolute (JUMP to subroutine) a

JSR (20)

1 OpCode, 3 bytes, 3 cycles

(different order from N6502)

2. Absolute Indexed Indirect (a, x)

JMP (7C)

1 OpCode, 3 bytes, 6 cycles

3a. Absolute , X a, x

ADC, AND, BIT, CMP, EOR, LDA, LDY,

ORA, SBC, STA, STZ

11 OpCodes, 3 bytes, 4,5 and 6 cycles

3b. Absolute, X(R-M-W) a, x

ASL, DEC, INC, LSR, ROL, ROR

6 OpCodes, 3 bytes, 7 cycles

4. Absolute, Y a, y

ADC, AND, CMP, EOR, LDA, LDX, ORA,

SBC, STA

9 OpCodes, 3 bytes, 4,5 and 6 cycles

5. Absolute Indirect (a)

JMP (6C)

1 OpCode, 3 bytes, 6 cycles

6. Accumulator A

ASL, DEC, INC, LSR, ROL, ROR

6 OpCodes, 1 byte, 2 cycles

7. Immediate #

ADC, AND, BIT, CLR, CMP, CPY, CPX,

EOR, LDA, LDX, LDY, ORA, SBC

13 OpCodes, 2 bytes, 2 and 5 cycles

8a. Implied i

CLC, CLD, CLI, CLV, DEX, DEY, INX,

INY, NOP, SEC, SED, SEI, TAX. TAY,

TXA. TSX. TXS, TYA

18 OpCodes, 1 byte, 2 cycles

Table 6-5 Instruction Timing Chart

Note Cycle VPB MLB SYNC Address Bus

1

1

1

1

(6)

2

1

1

0

3

1

1

0

4

1

1

0

PC

PC+1

PC+2

AA

1

1

1

1

2

1

1

0

3

1

1

0

4

1

0

0

5

1

0

0

6

1

0

0

1

1

1

1

2

1

1

0

3

1

1

0

1

1

1

1

1

1

1

1

2

1

1

0

3

1

1

0

4

1

1

0

5

1

1

0

6

1

1

0

1

1

1

1

1

1

1

1

2

1

1

0

(1)

3

1

1

0

4

1

1

0

5

1

1

0

6

1

1

0

1

1

1

1

1

1

1

1

2

1

1

0

(1)

3

1

1

0

(6)

4

1

1

0

(1)

1

1

1

1

2

1

1

0

3

1

1

0

4

1

1

0

5

1

0

0

6

1

0

0

7

1

0

0

1

1

1

1

(1)

2

1

1

0

(6)

3

1

1

0

4

1

1

0

1

1

1

1

2

1

1

0

3

1

1

0

4

1

1

0

5

1

1

0

6

1

1

0

1

1

1

1

1

1

1

1

2

1

1

0

PC

PC+1

PC+2

AA

AA

AA

PC

PC+1

PC+2

New PC

PC

PC+1

S

S

S+1

PC+2

New PC

PC

PC+1

PC+2

PC+2

AA+X

AA+X+1

New PC

PC

PC+1

PC+2

AA+X

PC

PC+1

PC+2

AAH,AAL+X

AA+X

AA+X+1

AA+X

PC

PC+1

PC+2

AA+Y

PC

PC+1

PC+2

PC+2

0,AA

0,AA+1

New PC

PC

PC+1

1

1

1

1

(6)

2

1

1

0

PC

PC+1

1

1

1

1

2

1

1

0

PC

PC+1

W65C02S Datasheet

Data Bus

OpCode

AAL

AAH

Data

OpCode

AAL

AAH

Data

IO

Data

OpCode

New PCL

New PCH

New OpCode

OpCode

New PCL

IO

PCH

PCL

New PCH

New OpCode

OpCode

AAL

AAH

IO

New PCL

New PCH

OpCode

OpCode

AAL

AAH

Data

OpCode

AAL

AAH

IO

Data

IO

Data

OpCode

AAL

AAH

Data

OpCode

AAL

AAH

IO

New PCL

New PCH

OpCode

OpCode

IO

OpCode

ID

RWB

1

1

1

1/0

1

1

1

1

1

0

1

1

1

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1/0

1

1

1

1

1

1

0

1

1

1

1/0

1

1

1

1

1

1

1

1

1

1

1

OpCode

1

IO

1

The Western Design Center, Inc.

W65C02S Datasheet

32

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