V54C365804VDL-75 データシートの表示（PDF） - Mosel Vitelic Corporation

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V54C365804VDL-75

HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8

Mosel Vitelic Corporation  

MOSEL VITELIC

Capacitance*

TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz

Symbol Parameter

Max. Unit

CI1

Input Capacitance (A0 to A11)

5 pF

CI2

Input Capacitance

5 pF

RAS, CAS, WE, CS, CLK, CKE, DQM

CIO

CCLK

Output Capacitance (I/O)

Input Capacitance (CLK)

6.5 pF

4 pF

*Note:Capacitance is sampled and not 100% tested.

Block Diagram

Column Addresses

A0 - A8, AP, BA0, BA1

Column address

counter

Column address

buffer

Row Addresses

A0 - A11, BA0, BA1

Row address

buffer

V54C365804VD(L)

Refresh Counter

Row decoder

Memory array

Bank 0

4096 x 512

x 8 bit

Row decoder

Memory array

Bank 1

4096 x 512

x 8 bit

Row decoder

Memory array

Bank 2

4096 x 512

x 8 bit

Row decoder

Memory array

Bank 3

4096 x 512

x 8 bit

Input buffer Output buffer

I/O1-I/O8

Control logic & timing generator

V54C365804VD(L) Rev. 0.9 September 2001

3

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