V436664Z24VBBG-10PC データシートの表示（PDF） - Mosel Vitelic Corporation
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V436664Z24VBBG-10PC
Mosel Vitelic Corporation
V436664Z24VBBG-10PC Datasheet PDF : 12 Pages
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MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte Num-
ber
Function Described
SPD Entry Value
29
Minimum RAS to CAS Delay tRCD
30
Minimum RAS Pulse Width tRAS
31
Module Bank Density (Per Bank)
15 ns/20 ns
42 ns/45 ns
256 Mbyte
64
SDRAM Input Setup Time
1.5 ns/2.0 ns
33
SDRAM Input Hold Time
0.8 ns/ 1.0 ns
34
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
35
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
62-61
Superset Information (May be used in Future)
62
SPD Revision
Revision 2 / 1.2
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
Mosel Vitelic
65-71
Manufacturer’s JEDEC ID Code (cont.)
72
Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436664Z24V
91-92
PCB Identification Code
Current PCB Revision
93
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
99-125 Reserved
126
Intel Specification for Frequency
127
Supported Frequency
128+
Unused Storage Location
-75PC
0F
2A
40
15
08
15
08
00
02
FE
40
00
00
64
00
V436664Z24V
Hex Value
-75
14
2D
40
15
08
15
08
00
02
43
40
00
-10PC
14
2D
40
20
10
20
10
00
12
B1
40
00
00
00
64
64
00
00
V436664Z24V Rev. 1.2 February 2002
5
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