TSC80251A1-B12ICD データシートの表示（PDF） - Temic Semiconductors

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TSC80251A1-B12ICD

Extended 8–bit Microcontroller with Analog Interfaces

Temic Semiconductors 

TSC 80251A1

Extended 8–bit Microcontroller with Analog Interfaces

The TSC80251A1 products are derivatives of the TEMIC Application Specific Microcontroller

family based on the extended 8–bit C251 Architecture described below.

This family of products are tailored to Microcontroller applications requiring analog interface

structures.

Three major peripheral blocks have been implemented to provide this facility to the designer:

D Analog to Digital Converter: 4 inputs at 8–bit resolution.

D Pulse Measurement Unit (PMU): 3 modules used to interface to smart analog sensors.

D Event and Waveform Controller (EWC): 5 programmable Counters e.g. for Pulse Width

Modulation (PWM) or Compare/Capture functions.

1.1. Application focus

Typical applications for these products are CD–ROM, Card or Barcode readers, Monitors, Car

Navigation Systems, Airbag and Brake Systems, as well as all kinds of Industrial Control and

Measurement Equipment. With the high instruction throughput, the TSC80251A1 products are

focussing on all high–end 8–bit to 16–bit applications. They are also well suited to systems where

a lower operating frequency is needed to reduce power consumption or Radio Frequency

Interference (RFI), while maintaining a high level of CPU–power.

1.2. C251 Architecture

The C251 Architecture at its lowest performance level, is Binary Code compatible with the 80C51

Architecture. Due to a 3–stage Instruction Pipeline, the CPU–Performance is increased by up to 5

times, using existing 80C51 code without any modification.

Using the new C251 Instruction Set, the performance will be increased by up to 15 times, at the same

clock rate.

This performance enhancement is based on the 16–bit instruction bus and additional internal 8 and

16–bit data busses. The 24–bit address bus will allow an extension of the address space up to 16

Mbytes for future derivatives.

Programming flexibility and C–code efficiency are both increased by the Register–based

Architecture, the 64–Kbyte extended stack space, combined with the new Instruction Set.

Combining the above features of the C251 core, the final code size could be reduced by a factor of

3, compared to an 80C51 implementation.

All technical information in this document about core features are related to the core revision A

(A–stepping). A new core revision, B/C (B–stepping) is presently in preparation.

Both versions are upward compatible, so that no problem will appear if an A–stepping product is

replaced by a B–stepping one.

The major differences are some additional features in the configuration bytes and a modified

emulator interface which will not affect existing application.

1.

Rev. B (20/09/96)

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