TS555IPT データシートの表示（PDF） - STMicroelectronics

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TS555IPT

Low power single CMOS timer

STMicroelectronics 

Schematic diagrams

TS555

Note:

Figure 2. Block diagram

VCC

8

Reset

4

R

Threshold 6

Control

Voltage 5

Trigger 2

+

-A

R

+

-

B

R

1

Ground

R1

Q

R

S

TS555

3 Output

7 Discharge

Table 3. Functions table

Reset

Trigger

Low

High

High

High

x

Low

High

High

Threshold

x

x

High

Low

LOW: level voltage ≤ minimum voltage specified.

HIGH: level voltage ≥ maximum voltage specified.

x: irrelevant.

Output

Low

High

Low

Previous state

4/20

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