IDT72261L10PF データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDT72261L10PF

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

tCLKH

tCLKL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

WEN

1

tENS

tENH

PAF

D - (m+1) words in

FIFO memory

2

1

tPAF

D - m words in

FIFO memory

(1,2)

(3)

tSKEW2

2

tPAF

D-(m+1)

Words in

FIFO

memory

RCLK

tENS

tENH

REN

3036 drw 18

NOTES:

1. PAF offset = m, D = 16,384 for IDT72261, 32,768 words for IDT72271.

2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested

to the output register (no read operation necessary), it is not included in the FIFO memory count.

3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH (after one WCLK cycle plus tPAF). If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.

Figure 15. Programmable Almost Full Flag Timing (IDT Standard and FWFT modes)

WCLK

WEN

HF

RCLK

REN

tCLKH

tCLKL

D/2 words

tENS tENH

tHF

D/2 + 1 words

tHF

tENS

NOTES:

1. D = maximum FIFO depth = 16,384 for IDT72261, 32,768 words for IDT72271.

Figure 16. Half - Full Flag Timing (IDT Standard and FWFT modes)

D/2 words

3036 drw 19

23

Share Link: