
STM690/704/795/802/804/805/806
Figure 28. RESET Response Time (Assertion)
6
VCC
5
4
3
VRST
2
1
0
2µs/div
Figure 29. Power-fail Comparator Response Time (Assertion)
6
5
4
3
PFI
2
PFO
1
0
2µs/div
AI09152
1.45
1.40
1.35
1.30
1.25
1.20
1.15
AI09153
18/31