SP8542AN データシートの表示（PDF） - Signal Processing Technologies
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SP8542AN Datasheet PDF : 16 Pages
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TIMING CHARACTERISTICS
(Typical @ 25°C with VDD = +5V, unless otherwise noted)
PARAMETER
Thoughput Time (tTP=tA+tC)
Acquisition Time (tA) (2 SCLK Periods)
Conversion Time (tC) (15 SCLK Periods)
SCLKLow Pulse Width (tSKL)
SCLK High Pulse Width (tSKH)
SCLK Period (tSKT)
Setup Time DIN to SCLK Rising (tDISU)
Hold Time from SCLK Rising to DIN (tDIH).
Buss Relinquish Time (tBR)
Setup Time -SCLK Falling to CSN Falling (tCSSU)
CSN Low Before SCLK Rises (tCS)
SCLK Falling to Data Valid (tSD)
CSN Falling to STATUS Rising (tDCS)
SCLK 17Falling to Status Rising Free Run (tDSS)
SCLK16 Falling to Status Falling ( tDSE)
Delay SD Low to initiate Conversion (tPU)
Aperture Delay Slave-Mode (tAPC)
Aperture Delay Free-Running Mode (tAPS)
MIN.
4.25
400
3.75
110
110
250
0
5
10
90
TYP.
500
125
125
45
50
69
70
45
5
30
35
MAX.
UNIT
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
COND.
SP8542/8544DS/01
SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's
9
© Copyright 2000 Sipex Corporation
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