SC2434EVB データシートの表示（PDF） - Semtech Corporation

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SC2434EVB

TriPhase Current Mode Controller with Power Good

Semtech Corporation 

SC2434

POWER MANAGEMENT

Applications Information (Cont.)

PCB Layout Consideration

Good layout is necessary for successful implementation of the SC2434 based 3 tri-phase topology. There are few

general rules:

· Reserve enough PCB space for the power supply (1.2~1.5 square inch for every 10A of load current);

· Place enough high frequency ceramic capacitors inside and around the CPU socket (please follow CPU manufacture’s

decoupling guideline);

· Place bulk output capacitors around the CPU socket as uniformly as possible. The connection copper between

these capacitors and the CPU socket must be short and wide to minimize inductance and resistance;

· Always place the high power parts first;

· Always use a ground plane or ground planes;

· Always try to minimize the stray inductance of the high pulsating current loop which is formed by input capacitors

and the MOSFET half-bridges.

The following layout guideline gives details on how to achieve a good layout:

· Input filter should contain mixed electrolytic capacitors and MLC capacitors. For every 20A of load current, use

about 10uF of MLC caps. Put MLC caps close to current sensing resistor;

· Use surface mount current sensing resistor (typically 3~5 mOhm in surface mount package with low temperature

coefficient and low package inductance, typically less than 0.3nH);

· Try to minimize the stray inductance from the current sensing resistor to the drains of the top FETs by using wide

trace (>0.5” wide and no more than 3” long). This trace can run on inner1 layer, for example, if the inner2 layer is

the ground plane, assuming the FETs are on the top layer. This arrangement forms so called strip line structure for

the pulsating power current, which yields least amount of stray inductance. The concept is depicted in Fig. 7;

· Keep the layout as electrically symmetrical as possible, as shown in Fig. 8, to avoid very uneven stray inductance

from the sensing resistor to the drains of the top FETs;

· Use a pair of closely paralleled traces to pick up the sensing voltage across the sensing resistor. The sensing traces

server as differential input to the OC+ and OC- pins of the SC2434 controller. These traces should run on a routing

layer (e.g., bottom layer for 4 layer PCB case) to avoid picking up strong AC magnetic field due to power current flow.

In this case, the differential sensing traces are shielded by the ground layer. The filter cap across the OC+ and OC-

pins should be placed as close as possible to the controller. Pay close attention that never allow power current

flowing on or running close by the sensing traces. Please see Fig. 8;

· Separate power ground from analog ground to prevent power current from running over the analog ground plane.

The SC2434 controller should be placed on the quite analog ground area. The analog ground should be single-

point connected to the PGND near the output capacitor or the CPU socket to provide best possible ground sense.

Refer to the application schematics for those components should be connected directly to the AGND (Vcc decoupling

caps, cap on BGOUT pin, resistors on OSCREF pin, DACREF pin, FB pin, and PGIN pin).

Rsense

MLC

VIA

D TOP FET S D BOT FET S

VIA

Ground Plane

Fig. 7 - Use MLC capacitors and strip line structure to minimize the stray inductance for the switching current loop.

 2005 Semtech Corp.

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