Philips Semiconductors
Dual standard PDC decoder
Objective specification
SAA5233
SYMBOL
PARAMETER
CONDITIONS
I2C-bus timing (see Fig.4)
fclk
SCL clock frequency
tBUF
bus free time between a
STOP and START
tHD;STA
tLOW
tHIGH
tSU;STA
repeated START hold time
SCL clock LOW time
SCL clock HIGH time
set-up time for a repeated
START
note 1
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
data hold time
data set-up time
SDA, SCL input rise time
SDA, SCL input fall time
set-up time for STOP
0.3VDD to 0.7VDD
0.7VDD to 0.3VDD
Note
1. After this time the first clock pulse is generated.
MIN.
TYP.
MAX.
UNIT
0
−
4.7
−
4.0
−
4.7
−
4.0
−
4.7
−
0
−
250
−
−
−
−
−
4.0
−
100
kHz
−
µs
−
µs
−
µs
−
µs
−
µs
−
ns
−
ns
1 000
ns
300
ns
−
µs
andbook, full pagewidth
SDA
t BUF
t LOW
SCL
SDA
MBC764
t HD;STA
tr
t HD;DAT
t SU;STA
tf
t HIGH
t SU;DAT
t SU;STO
June 1994
Fig.4 I2C-bus timing diagram.
9