PCF8563BS データシートの表示（PDF） - NXP Semiconductors.

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PCF8563BS

Real-time clock/calendar

NXP Semiconductors. 

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.8.2 Register Timer

Table 24. Timer - timer value register (address 0Fh) bit description

Bit

Symbol

Value

Description

7 to 0 TIMER[7:0] 00h to FFh

countdown period in seconds:

CountdownPeriod

=

-------------------------------n-------------------------------

SourceClockFrequency

where n is the countdown value

Table 25. Timer register bits value range

Bit

7

6

5

4

3

2

1

0

128

64

32

16

8

4

2

1

The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the

Timer_control register bit TE. The source clock for the timer is also selected by the

Timer_control register. Other timer properties such as interrupt generation are controlled

via the register Control_status_2.

For accurate read back of the count down value, it is recommended to read the register

twice and check for consistent results, since it is not possible to freeze the countdown

timer counter during read back.

8.9 EXT_CLK test mode

A test mode is available which allows for on-board testing. In such a mode it is possible to

set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit TEST1 in register Control_status_1. Then

pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the

signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is

divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into

a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP

must be cleared before the prescaler can operate again).

From a STOP condition, the first 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the test mode, no assumption as to the state of the prescaler can be made.

8.9.1 Operation example:

PCF8563

Product data sheet

1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).

2. Set STOP (Control_status_1, bit STOP = 1).

3. Clear STOP (Control_status_1, bit STOP = 0).

4. Set time registers to desired value.

All information provided in this document is subject to legal disclaimers.

Rev. 9 — 16 June 2011

© NXP B.V. 2011. All rights reserved.

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