
TIMING DIAGRAM
CLOCK
RESET
Q1
Q2
Q3
Q4
1234
8
16
32
64
128
Q6
Q7
EXPANDED LOGIC DIAGRAM
Q1
Q2
Q3
Q4
Q5
12
11
9
6
5
MC74HC4024
Q6
Q7
4
3
1
CLOCK
2
RESET
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
C
R
High–Speed CMOS Logic Data
5
DL129 — Rev 6
MOTOROLA