Electrical Characteristics: (Notes 2 and 3)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Logical “1” Input Voltage
Logical “1” Input Current
Logical “0” Input Voltage
Logical “0” Input Current
Input Clamp Voltage
Logical “1” Output Voltage
Output Short Circuit Current
VIH VCC = Min
2.0 − − V
IIH VCC = Max, VIN = 2.4V
VCC = Max, VIN = 5.5V
− − 40 μA
− − 1.0
VIL VCC = Min
− − 0.8 V
IIL VCC = Max, VIN = 0.4V
− −1.0 −1.6 mA
VCD VCC = Min, IIN = −12mA − − −1.5 V
VOH VCC = Min, IOUT = −800μ 2.4 − − V
IOS VCC = Max, VOUT = 0V, −25 − −70 mA
Note 4
Logical “0” Output Voltage
Supply Current
TRI−STATE I/O Current with
Inputs and Outputs Disabled
Propagation Delay to a Logical “0”
from Clock to Output
Propagation Delay to a Logical “0”
from Clear to Output
Propagation Delay to a Logical “1”
from Clock to Output
Delay from Disable to High
Impedance State
(from Logical “1” Level)
Delay from Disable to High
Impedance State
(from Logical “0” Level)
Delay from Disable to Logical
“1” Level
(from High Impedance State)
VOL VCC = Min, IOUT = 16mA − − 0.4 V
ICC VCC = Max
− − 120 mA
VCC = Max, VIN = 2.4V
VCC = Max, VIN = 0.4V
− − 40 μA
− − −40
tpd0 RL = 400Ω, CL = 50pF
TA = 25°C
− 23 35 ns
tpd0 RL = 400Ω, CL = 50pF
TA = 25°C
− 24 36 ns
tpd1 RL = 400Ω, CL = 50pF
TA = 25°C
− 25 38 ns
t1H RL = 400Ω, CL = 5.0pF
TA = 25°C
− 6.0 15 ns
t0H RL = 400Ω, CL = 5.0pF
TA = 25°C
− 15 25 ns
tH1 RL = 400Ω, CL = 50pF
TA = 25°C
− 20 30 ns
Delay from Disable to Logical
“0” Level
(from High Impedance State)
tH0 RL = 400Ω, CL = 50pF
TA = 25°C
− 17 25 ns
Maximum Clock Frequency
Enable to Clock Set−Up Time
Enable to Clock Set−Up Time
fMAX
tSO
tSI
RL = 400Ω, CL = 50pF
TA = 25°C
RL = 400Ω, CL = 50pF
TA = 25°C
RL = 400Ω, CL = 50pF
TA = 25°C
30 40 − MHz
20 13 − ns
20 12 − ns