NCP1027P100G(2015) データシートの表示（PDF） - ON Semiconductor

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NCP1027P100G
(Rev.:2015)

High-Voltage Switcher for Medium Power Offline SMPS Featuring Low Standby Power

ON Semiconductor 

NCP1027

Improving the Precision in Auto−Recovery OVP

Given the OVP variations the internal trip current

dispersion incur, it is sometimes more interesting to

explore a different solution, improving the situation to the

cost of a minimal amount of surrounding elements.

Figure 37 shows that adding a simple Zener diode on top

of the limiting resistor, offers a better precision since what

matters now is the internal 8.7 V VCC breakdown, plus the

Zener voltage. A resistor in series with the Zener diodes

keeps the maximum current in the VCC pin below the

maximum rating of 15 mA just before tripping the OVP.

VCC

Rlimit

+

D1

Laux

Ground

Figure 37. A simple Zener diode added in

parallel with Rlimit , allows for a better

precision OVP.

Over Power Compensation

Over Power Compensation or Protection (OPP)

represents a way to limit the effects of the propagation

delay when the converter is supplied from its highest input

voltage. The propagation delay naturally extends the

power capability of any current−limited converter.

Figure 38 explains why. The main parameter is the on

slope, that is to say, the pace at which the inductor current

grows−up when the power switch closes. For a flyback

controller, the slope is given by:

Son

+

Vin

Lp

(eq. 4)

where Lp is the transformer magnetizing/primary

inductance and Vin, the input voltage.

As the internal logic takes some time to react, the switch

gate shutdown does not immediately occur when the

maximum power limit is detected (just before activating

the overload protection circuit). Clearly speaking, it can

take up to 100 ns for the NCP1027 current sense

comparator to propagate through the various logical gates

before reaching the power switch and finally shutting it off.

This is the well−known propagation delay noted tprop.

Unfortunately, during this time, the current keeps growing

as Figure 38 depicts. The peak current will therefore be

troubled by this propagation delay. The formula to obtain

the final value is simply:

Ipeak,

final

+

Vin

Lp

tprop ) Ipeak, max

(eq. 5)

Figure 38. Internal logic blocks take a certain amount

of time before shutting off the driving pulses in

presence of an overcurrent event.

At low line, Son is relatively low and does not bother the

final peak value. The situation differs at high line and

induces a higher peak current. Therefore, the power supply

output power capability increases with the input voltage.

Let us a take a look at a simple example. Suppose the peak

current is 700 mA:

Lp = 1.0 mH

Vin lowline = 100 Vdc

Vin highline = 350 Vdc

Ipeak,max = 700 mA

tprop = 100 ns

Pout

+

1

2

I2peak,

final

FSWLph

(eq. 6)

Where: Fsw is the switching frequency and h the efficiency.

Usually h is bigger in high line conditions than in low line

conditions. This formula is valid for a Discontinuous

Conduction Mode flyback.

From Equation 5, we can calculate the final peak current

in both conditions:

Ipeak,final = (100/1m) x 100n + 700m = 710 mA at low line.

Ipeak,final = (350/1m) x 100n + 700m = 735 mA at high line.

From Equation 6, we can have an idea of the maximum

output power capability again, in both conditions with

respective low and high line efficiency numbers of 78%

and 82% for instance:

Pout,lowline = 0.5 0.712 1m 65k 0.78 = 12.8 W

Pout,highline = 0.5 0.7352 1m 65k 0.82 = 14.4 W

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