74ACT2708CW データシートの表示（PDF） - Fairchild Semiconductor

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74ACT2708CW

64 x 9 First-In, First-Out Memory

Fairchild Semiconductor 

Mode 5: With FIFO Empty, Shift-Out is Held HIGH

in Anticipation of Data

Sequence of Operation

1. FIFO is initially empty; Shift-Out goes HIGH.

2. Shift-In pulse loads data into the FIFO and IR falls. HF

rises propagation delay tX1 after the falling edge of SI.

3. OR rises a fall-through time of tFTO after the falling

edge of Shift-In, indicating that new data is ready to be

output.

4. Data arrives at output one propagation delay, tOD5,

after the falling edge of Shift-In.

5. OR goes LOW pulse width tOP after rising and HF

goes LOW pulse width tX3 after rising, indicating that

the FIFO is empty once more.

6. Shift-Out goes LOW, necessary to complete the Shift-

Out process.

Note: FULL is LOW; MRis HIGH; OE is LOW; tDOF = tFTO − tOD5. Data output transition—valid data arrives at output stage tDOF after OR is HIGH.

FIGURE 5. Modes of Operation Mode 5

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