MSM514260CSL-50 データシートの表示（PDF） - Oki Electric Industry
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MSM514260CSL-50 Datasheet PDF : 16 Pages
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¡ Semiconductor
MSM514260C/CSL
BLOCK DIAGRAM
RAS
LCAS
UCAS
A0 - A8
Timing
Generator
Column
9 Address
Buffers
WE
OE
I/O
Controller
I/O
Controller
9 Column Decoders
8
Output
Buffers
8
8
Input
Buffers
8
Internal
Address
Counter
Refresh
Control Clock
9
Row
Address 9
Buffers
Row
Deco-
ders
Word
Drivers
Sense Amplifiers
16
I/O
Selector 16
Memory
Cells
8
Input
Buffers
8
8
Output
Buffers
8
VCC
On Chip
VBB Generator
VSS
DQ1 - DQ8
DQ9 - DQ16
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS LCAS UCAS WE
OE
DQ1 - DQ8 DQ9 - DQ16
H
*
*
*
*
High-Z
High-Z
Standby
L
H
H
*
*
High-Z
High-Z
Refresh
L
L
H
H
L
L
H
L
H
L
L
L
L
H
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
Lower Byte Read
Upper Byte Read
Word Read
L
L
H
L
H
DIN
Don't Care Lower Byte Write
L
H
L
L
H
Don't Care
DIN
Upper Byte Write
L
L
L
L
H
DIN
DIN
Word Write
L
L
L
H
H
High-Z
High-Z
—
*: "H" or "L"
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