MPC9352 データシートの表示（PDF） - Motorola => Freescale
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MPC9352 Datasheet PDF : 16 Pages
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Freescale Semiconductor, Inc.
MPC9352
Example Configurations for the MPC9352
Figure 3. MPC9352 Default Configuration
Figure 4. MPC9352 Zero Delay Buffer Configuration
fref = 100 MHz
CCLK
QA0
QA1
QA2
QA3
FB_IN
QA4
FSELA
FSELB
QB0
QB1
QB2
FSELD
QB3
F_RANGE
QC0
QC1
MPC9352
100 MHz (Feedback)
100 MHz
100 MHz
200 MHz
fref = 62.5 MHz
VCC
CCLK
QA0
QA1
QA2
QA3
FB_IN
QA4
FSELA
FSELB
QB0
QB1
QB2
FSELC
QB3
F_RANGE
QC0
QC1
MPC9352
62.5 MHz (Feedback)
62.5 MHz
62.5 MHz
62.5 MHz
MPC9352 default configuration (feedback of QB0 = 100 MHz).
All control pins are left open.
Frequency range
Input
QA outputs
QB outputs
QC outputs
Min
50 MHz
50 MHz
50 MHz
100 MHz
Max
100 MHz
10 MHz
100 MHz
200 MHz
MPC9352 zero–delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs
are locked in frequency and phase to the input clock.
Frequency range
Input
QA outputs
QB outputs
QC outputs
Min
50 MHz
50 MHz
50 MHz
50 MHz
Max
100 MHz
10 MHz
100 MHz
100 MHz
Figure 5. MPC9352 Default Configuration
fref = 33.3 MHz
VCC
VCC
VCC
CCLK
QA0
QA1
QA2
QA3
FB_IN
QA4
FSELA
FSELB
QB0
QB1
QB2
FSELC
QB3
F_RANGE
QC0
QC1
MPC9352
33.3 MHz (Feedback)
33.3 MHz
50 MHz
100 MHz
MPC9352 configuration to multiply the reference frequency
by 3, 3÷2 and 1. PLL feedback of QA4 = 33.3 MHz.
Frequency range
Input
QA outputs
QB outputs
QC outputs
Min
25 MHz
50 MHz
50 MHz
100 MHz
Max
50 MHz
10 MHz
100 MHz
200 MHz
Figure 6. MPC9352 Zero Delay Buffer Config. 2
fref = 33.3 MHz
VCC
VCC
CCLK
QA0
QA1
QA2
QA3
FB_IN
QA4
FSELA
FSELB
QB0
QB1
QB2
FSELC
QB3
F_RANGE
QC0
QC1
MPC9352
33.3 MHz (Feedback)
33.3 MHz
33.3 MHz
33.3 MHz
MPC9352 zero–delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency range
Input
QA outputs
QB outputs
QC outputs
Min
25 MHz
25 MHz
25 MHz
25 MHz
Max
50 MHz
50 MHz
50 MHz
50 MHz
TIMING SOLUTIONS
For More Informa9tion On This Product,
Go to: www.freescale.com
MOTOROLA
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