MPC9352 データシートの表示（PDF） - Motorola => Freescale

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MPC9352

3.3V / 2.5V 1:11 LVCMOS Zero Delay Clock Generator

Motorola => Freescale 

Freescale Semiconductor, Inc.

MPC9352

Table 1: PIN CONFIGURATION

Pin

CCLK

FB_IN

I/O

Input

Input

F_RANGE

FSELA

Input

Input

FSELB

FSELC

Input

Input

PLL_EN

Input

MR/OE

QA0–4, QB0–3, QC0–1

GND

VCCA

Input

Output

Supply

Supply

VCC

Supply

Type

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

Ground

VCC

VCC

Function

PLL reference clock signal

PLL feedback signal input, connect to an output

PLL frequency range select

Frequency divider select for bank A outputs

Frequency divider select for bank B outputs

Frequency divider select for bank C outputs

PLL enable/disable

Output enable/disable (high–impedance tristate) and device reset

Clock outputs

Negative power supply

PLL positive power supply (analog power supply). It is recommended to use an

external RC filter for the analog power supply pin VCCA. Please see

applications section for details.

Positive power supply for I/O and core

Table 2: FUNCTION TABLE

Control

Default

0

1

F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.

See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.

F_RANGE

0

VCO ÷ 1 (High input frequency range)

VCO ÷ 2 (Low input frequency range)

FSELA

FSELB

FSELC

0

Output divider ÷ 4

0

Output divider ÷ 4

0

Output divider ÷ 2

Output divider ÷ 6

Output divider ÷ 2

Output divider ÷ 4

MR/OE

0

Outputs enabled (active)

Outputs disabled (high–impedance state) and

reset of the device. During reset, the PLL

feedback loop is open and the VCO is operating

at its lowest frequency. The MPC9352 requires

reset at power–up and after any loss of PLL

lock. Loss of PLL lock may occur when the

external feedback path is interrupted. The length

of the reset pulse should be greater than two

reference clock cycles (CCLK).

PLL_EN

0

Normal operation mode with PLL enabled.

Test mode with PLL disabled. CCLK is

substituted for the internal VCO output.

MPC9352 is fully static and no minimum

frequency limit applies. All PLL related AC

characteristics are not applicable.

TIMING SOLUTIONS

For More Informa3tion On This Product,

Go to: www.freescale.com

MOTOROLA

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