MH32S64PHB-8 データシートの表示（PDF） - MITSUBISHI ELECTRIC

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MH32S64PHB-8

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32S64PHB -7,-8,-10

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

[ Write Interrupted by Precharge ]

Burst write operation can be interrupted by precharge of the same bank. Random

column access is allowed. Because the write recovery time(tWR) is required from the

last data to PRE command.

Write Interrupted by Precharge (BL=4)

CK

Command

A0-9,11

A10

A11

BA0,1

Write

Yi

0

00

PRE

tWR

0

00

ACT

tRP

Xb

Xb

Xb

00

DQMB0-7

DQ

Dai0 Dai1 Dai2

[ Write Interrupted by Burst Terminate ]

A burst terminate command TBST can terminate burst write operation. In this case,

the write recovery time is not required and the bank remains active (Please see the

waveforms below).The WRITE to TBST minimum interval is 1CK.

CK

Command

A0-9

A10

BA0,1

DQMB0-7

DQ

Write Interrupted by Burst Terminate (BL=4)

Write

Yi

0

0

TBST

Dai0 Dai1 Dai2

MIT-DS-0301-0.0

MITSUBISHI

ELECTRIC

( 26 / 55 )

11/Jan. /1999

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