MH32S64PHB-8 データシートの表示（PDF） - MITSUBISHI ELECTRIC

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MH32S64PHB-8

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32S64PHB -7,-8,-10

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

BURST INTERRUPTION

[ Read Interrupted by Read ]

Burst read option can be interrupted by new read of any bank. Random column access is

allowed. READ to READ interval is minimum 1 CK

Read Interrupted by Read (BL=4, CL=3)

CK

Command

A0-9

A10

A11

BA0,1

DQ

READ READ

Yi Yj

00

READ

Yk

0

READ

Yl

0

00 00

10

01

Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3

[ Read Interrupted by Write ]

Burst read operation can be interrupted by write of the same or the other bank. Random

column access is allowed. In this case, the DQ should be controlled adequately by using the

DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after

WRITE assertion.

Read Interrupted by Write (BL=4, CL=3)

CK

Command

READ

Write

A0-9

Yi

Yj

A10

0

0

A11

BA0,1

0

0

DQMB0-7

Q

D

MIT-DS-0301-0.0

Qai0

Daj0 Daj1 Daj2 Daj3

DQM control Write control

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11/Jan. /1999

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