MH16S64AMA-12 データシートの表示（PDF） - MITSUBISHI ELECTRIC

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MH16S64AMA-12

1073741824-BIT (16777216 - WORD BY 64-BIT) SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

[ Write Interrupted by Write ]

Burst write operation can be interrupted by new write of the same or the other bank.

Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.

Write Interrupted by Write (BL=4)

CK

Command

A0-9,11

A10

BA0,1

DQ

Write Write

Write

Write

Yi Yj

Yk

Yl

00

0

0

00

1

0

Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3

[ Write Interrupted by Read ]

Burst write operation can be interrupted by read of the same or the other bank.

Random column access is allowed. WRITE to READ interval is minimum 1 CK. The

input data on DQ at the interrupting READ cycle is "don't care".

Write Interrupted by Read (BL=4, CL=3)

CK

Command

Write READ

Write

READ

A0-9,11

Yi Yj

Yk

Yl

A10

00

0

0

BA0,1

DQMB0-7

00

0

1

DQ

Dai0

Qaj0 Qaj1

Dak0 Dak1

Qbl0

MIT-DS-0127-0.0

MITSUBISHI

ELECTRIC

( 23 / 52 )

4. Mar.1997

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