MC14538BCL データシートの表示（PDF） - Motorola => Freescale
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MC14538BCL Datasheet PDF : 10 Pages
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VDD
RX
2 (14)
CX
1 (15)
4 (12)
A
5 (11)
B
3 (13)
RESET
VDD
P1
Vref1
N1
VSS
+
–C1 ENABLE
+ ENABLE
C2
Vref2 –
CONTROL
QR
QR
S RESET LATCH R
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
RQ
OUTPUT
LATCH
SQ
6 (10)
7 (9)
NOTE: Pins 1, 8 and 15 must
be externally grounded
500 pF
VDD
ID
0.1 µF
CERAMIC
RX
VSS CX
RX′
CX′
VSS
Vin
A
CX/RX
B
RESET
A′
B′
RESET′
Q
CL
Q
Q′
CL
Q′
CL
CL
VSS
20 ns
Vin
90%
10%
20 ns
VDD
0V
Figure 2. Power Dissipation Test Circuit and Waveforms
VSS
PULSE
GENERATOR
PULSE
GENERATOR
PULSE
GENERATOR
VDD
RX
RX′
CX
CX′
A
CX/RX
* CL = 50 pF
VSS
B
RESET
A′
B′
RESET′
Q
CL
Q
Q′
CL
CL
Q′
CL
VSS
INPUT CONNECTIONS
Characteristics
Reset
A
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD
PG1
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD
VSS
tPLH(R), tPHL(R),
tWH, tWL
PG3 PG1
* Includes capacitance of probes,
wiring, and fixture parasitic.
NOTE: Switching test waveforms
for PG1, PG2, PG3 are shown
In Figure 4.
PG1 =
PG2 =
PG3 =
Figure 3. Switching Test Circuit
B
VDD
PG2
PG2
MC14538B
4
MOTOROLA CMOS LOGIC DATA
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