MC100LVELT22DT データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

MC100LVELT22DT

3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

ON Semiconductor 

MC100LVELT22

Q0 1

Q0 2

LVPECL

Q1 3

8 VCC

7 D0

LVTTL/

LVCMOS

6 D1

Q1 4

5 GND

Table 1. PIN DESCRIPTION

PIN

Qn, Qn

D0, D1

VCC

GND

EP

FUNCTION

LVPECL Differential Outputs

LVTTL/LVCMOS Inputs

Positive Supply

Ground

Exposed pad must be connected

to a sufficient thermal conduit.

Electrically connect to the most

negative supply or leave floating

open.

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

EP

Table 2. ATTRIBUTES

Characteristics

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model

Machine Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Flammability Rating

Oxygen Index: 28 to 34

Transistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Value

N/A

N/A

> 4 kV

> 200 V

Level 1

UL 94 V−0 @ 0.125 in

164

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VCC

Positive Power Supply

VI

Input Voltage

Iout

Output Current

GND = 0 V

GND = 0 V

Continuous

Surge

VI  VCC

7

V

7

V

50

mA

100

mA

TA

Operating Temperature Range

Tstg

Storage Temperature Range

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SO−8

SO−8

−40 to +85

−65 to +150

190

130

°C

°C

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case) std bd

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SO−8

TSSOP−8

TSSOP−8

41 to 44 ± 5%

185

140

°C/W

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case) std bd

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8

DFN8

DFN8

41 to 44 ± 5%

129

84

°C/W

°C/W

°C/W

Tsol

Wave Solder

Pb <2 to 3 sec @ 248°C

Pb−Free <2 to 3 sec @ 260°C

265

°C

265

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

http://onsemi.com

2

Share Link: