MB91266PMC-G-XXXE1 データシートの表示（PDF） - Fujitsu

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MB91266PMC-G-XXXE1

(MB91265A Series) 32-bit Proprietary Microcontrollers

Fujitsu 

MB91265 Series

Notes on the PS register

As the PS register is processed by some instructions in advance, exception handling below may cause the

interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register

to be updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it

performs operations before and after the EIT as specified in either case.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event

or emulator menu :

1) The D0 and D1 flags are updated in advance.

2) An EIT handling routine (user interrupt or emulator) is executed.

3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are updated

to the same values as in 1).

• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed

to allow the interrupt.

1) The PS register is updated in advance.

2) An EIT handling routine (user interrupt) is executed.

3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the

same value as in 1).

Watchdog Timer

The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.

The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from

being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on

operating programs until it resets the CPU.

As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops

program execution.

For those conditions to which this exception applies, see the function description of watchdog timer.

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