MB90098APF データシートの表示（PDF） - Fujitsu

部品番号

コンポーネント説明

メーカー

MB90098APF

On-Screen Display Controller

Fujitsu 

MB90098A

(Continued)

Com-

mand

No.

Function

Command Code/Data

15-12 11 10 9

8

7

6

5

4

3

2

1

0

9-0

Sprite character

control 3

1001 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

9-1

Sprite character

control 4

1001 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

11-0

Synchronization

control

1011 0 0 0 0 EG1 1 0 0 0 0 0 0

11-2 Dot clock control 1 1011 1 0 DO 0 0 0 0 0 0 0 0 0

13-0

Input/output pin

control 1

1101 0 0 0 VHE HE 0 0 0 0 0 DBX DCX

13-1

Input/output pin

control 2

1101 0 1 0 0 0 0 0 0 0 IHX IVX IDX

14-0

CROM transfer start

address 1

1110

0

0

0

0

0

0 TSD TSC TSB TSA TS9 TS8

14-1

CROM transfer start

address 2

1110

0

0

1

0 TS7 TS6 TS5 TS4 TS3 TS2 TS1 0

14-2

CROM transfer end

address 1

1110

0

1

0

0

0

0 TED TEC TEB TEA TE9 TE8

14-3

CROM transfer end

address 2

1110

0

1

1 TSV TE7 TE6 TE5 TE4 TE3 TE2 TE1 1

Note : When a reset signal is input (L level signal input to the RESET pin) , the screen output control 1A bits SDS,

UDS, PDS, DSP and the input/output pin control 1 bits DBX and DCX are initialized to “0.” Other register

bits and VRAM contents are undefined.

After reset input/release is completed, set all register bits except for the command ROM transfer address

settings (commands 14-0, 14-1, 14-2, 14-3) and set all VRAM settings (character data and row control data) .

18

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