MB15E07SL(1998) データシートの表示（PDF） - Fujitsu

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MB15E07SL
(Rev.:1998)

Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler

Fujitsu 

MB15E07SL

s FUNCTIONAL DESCRIPTION

1. Pulse Swallow Function

The VCO output frequency can be calculated using the following equation:

fVCO = [(M × N) + A] × fOSC ÷ R (A < N)

fVCO : Output frequency of external voltage controlled oscillator (VCO)

N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)

fOSC : Output frequency of the reference frequency oscillator

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

M : Preset divide ratio of modulus prescaler (32 or 64)

2. Serial Data Input

Serial data is entered using the Data, Clock, and LE pins. The serial data controls the programmable reference

counter and the programmable counter separately.

Binary serial data is entered through the Data pin when the LE pin is held low. One bit of data is shifted into the

shift register on the rising edge of the Clock. When the LE signal pin is taken high, entered data is latched into the

appropriate counters according to the control bit setting as follows:

Table 1. Control Bit

Control bit (CNT)

H

L

Destination of serial data

For the programmable reference counter latch

For the programmable counter latch

(1) Shift Register Configuration

Programmable Reference Counter

LSB

Data Flow

MSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CRRRRRRRRRRRRRR

N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SW FC LDS CS

T

CNT

R1 to R14

SW

FC

LDS

CS

: Control bit

[Table 1]

: Divide ratio setting bits for the programmable reference counter (3 to 16,383) [Table 2]

: Divide ratio setting bit for the prescaler (32/33 or 64/65)

[Table 5]

: Phase control bit for the phase comparator

[Table 8]

: LD/fOUT signal select bit

[Table 7]

: Charge pump current select bit

[Table 6]

Note: Input data with MSB first.

8

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