MAX5802AAUBT(2012) データシートの表示（PDF） - Maxim Integrated

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MAX5802AAUBT
(Rev.:2012)

Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface

Maxim Integrated 

MAX5800/MAX5801/MAX5802

Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output

DACs with Internal Reference and I2C Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical

values are at TA = +25NC.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SDA and SCL Receiving

Rise Time

tr

20 +

CB/10

300

ns

SDA and SCL Receiving

Fall Time

tf

20 +

CB/10

300

ns

SDA Transmitting Fall Time

Setup Time for STOP Condition

Bus Capacitance Allowed

Pulse Width of Suppressed Spike

CLR Removal Time Prior to a

Recognized START

tf

tSU;STO

CB

tsp

VDD = 2.7V to 5.5V

tCLRSTA

20 +

CB/10

250

ns

0.6

Fs

10

400

pF

50

ns

100

ns

CLR Pulse Width Low

tCLPW

20

ns

Note 2: Limits are 100% production tested at TA = +25NC and/or TA = +125NC. Limits over the operating temperature range and

relevant supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25NC and are

not guaranteed.

Note 3: DC Performance is tested without load.

Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.

Note 5: Gain and offset calculated from measurements made with VREF = VDD at codes 30 and 4065 for MAX5802, codes 8 and

1016 for MAX5801, and codes 2 and 254 for MAX5800.

Note 6: Subject to zero and full-scale error limits and VREF settings.

Note 7: Measured with the DAC outputs at midscale with one channel transitioning 0 to full scale.

Note 8: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will

be ignored.

Note 9: Guaranteed by design.

Note 10: Both channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO.

Note 11: An unconnected condition on the ADDR pin is sensed via a resistive pullup and pulldown operation; for proper

operation, the ADDR pin should be tied to VDDIO, GND, or left unconnected with minimal capacitance.

SDA

tf

SCL

tCLPW

S

tLOW

tHD;STA

tSU;DAT

tr

tf

tHD;STA

tHD;DAT

tHIGH

tSU;STA

Sr

tSP

tr

tBUF

tSU;STO

P

S

CLR

tCLRSTA

Figure 1. I2C Serial Interface Timing Diagram

Maxim Integrated

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