MAX531ACSD データシートの表示（PDF） - Maxim Integrated

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MAX531ACSD

+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs

Maxim Integrated 

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

+5V

REFIN

REFOUT

BIPOFF

33µF

MAX531

RFB

AGND

DGND

VOUT

VOUT

-5V

Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)

Table 3. Bipolar (Offset Binary) Code

Table (-VREFIN to +VREFIN Output)

INPUT

1111 1111 1111

1000 0000 0001

1000 0000 0000

0111 1111 1111

0000 0000 0001

0000 0000 0000

OUTPUT

2047

(+VREFIN) 2048

(+VREFIN)

1

2048

0V

1

(-VREFIN) 2048

2047

(-VREFIN) 2048

2048

(-VREFIN) 2048 = -VREFIN

Single-Supply Linearity

As with any amplifier, the MAX531/MAX538/MAX539’s

output buffer can be positive or negative. When the off-

set is positive, it is easily accounted for (Figure 10).

However, when the offset is negative, the buffer output

cannot follow linearly when there is no negative supply.

In that case, the amplifier output (VOUT) remains at

ground until the DAC voltage is sufficient to overcome

the offset and the output becomes positive.

Normally, linearity is measured after accounting for

zero error and gain error. Since, in single-supply opera-

tion, the actual value of a negative offset is unknown, it

cannot be accounted for during test. Additionally, the

output buffer amplifier exhibits a nonlinearity near-zero

output when operating with a single supply. To account

for this nonlinearity in the MAX531/MAX538/MAX539,

linearity and gain error are measured from code 11 to

code 4095. The output buffer’s offset and nonlinear

behavior do not affect monotonicity, and these DACs

are guaranteed monotonic starting with code zero. In

dual-supply operation, linearity and gain error are mea-

sured from code 0 to 4095.

Power-Supply Bypassing and

Ground Management

Best system performance is obtained with printed cir-

cuit boards that use separate analog and digital

ground planes. Wire-wrap boards are not recommend-

ed. The two ground planes should be connected

together at the low-impedance power-supply source.

DGND and AGND should be connected together at the

chip. For the MAX531 in single-supply applications,

connect VSS to AGND at the chip. The best ground

connection may be achieved by connecting the DAC’s

DGND and AGND pins together and connecting that

point to the system analog ground plane. If the DAC’s

DGND is connected to the system digital ground, digi-

tal noise may get through to the DAC’s analog portion.

Bypass VDD (and VSS in dual-supply mode) with a

0.1µF ceramic capacitor, connected between VDD and

AGND (and between VSS and AGND). Mount with short

leads close to the device. Ferrite beads may also be

used to further isolate the analog and digital power

supplies.

Figures 11a and 11b illustrate the grounding and

bypassing scheme described.

Saving Power

When the DAC is not being used by the system, mini-

mize power consumption by setting the appropriate

code to minimize load current. For example, in bipolar

mode, with a resistive load to ground, set the DAC

code to mid-scale (Table 3). If there is no output load,

minimize internal loading on the reference by setting

the DAC to all 0s (on the MAX531, use CLR). Under this

condition, REFIN is high impedance and the op amp

operates at its minimum quiescent current. Due to

these low current levels, the output settling time for an

input code close to 0 typically increases to 60µs (no

more than 100µs).

12 ______________________________________________________________________________________

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