MAX5156BEEE データシートの表示（PDF） - Maxim Integrated

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MAX5156BEEE

Low-Power, Dual, 12-Bit Voltage-Output DACs with Configurable Outputs

Maxim Integrated 

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

______________________________________________________________Pin Description

PIN NAME

FUNCTION

1

AGND Analog Ground

2

OUTA DAC A Output Voltage

3

FBA

DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier.

4

REFA Reference for DAC A

5

CL

Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V.

6

CS

Chip-Select Input

7

DIN

Serial Data Input

8

SCLK Serial Clock Input

9

DGND Digital Ground

10

DOUT Serial Data Output

11

UPO User-Programmable Output

12

PDL

Power-Down Lockout. The device cannot be powered down when PDL is low.

13

REFB Reference Input for DAC B

14

FBB

DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier.

15

OUTB DAC B Output Voltage

16

VDD

Positive Power Supply

_______________Detailed Description

The MAX5156/MAX5157 dual, 12-bit, voltage-output

DACs are easily configured with a 3-wire serial inter-

face. These devices include a 16-bit data-in/data-out

shift register, and each DAC has a double-buffered

input comprised of an input register and a DAC register

(see Functional Diagram). Both DACs use an inverted

R-2R ladder network that produces a weighted voltage

proportional to the input voltage value. Each DAC has

its own reference input to facilitate independent full-

scale values. Figure 1 depicts a simplified circuit dia-

gram of one of the two DACs.

Reference Inputs

The reference inputs accept both AC and DC values

with a voltage range extending from 0V to (VDD - 1.4V).

Determine the output voltage using the following equa-

tion:

VOUT = VREF x NB / 4096

where NB is the numeric value of the DAC’s binary input

code (0 to 4095) and VREF is the reference voltage.

The reference input impedance ranges from 14kΩ (1554

hex) to several giga ohms (with an input code of 0000

hex). This reference input capacitance is code depen-

dent and typically ranges from 15pF with an input code

of all zeros to 50pF with a full-scale input code.

R

2R 2R

D0

R

R

2R

2R

2R

D9

D10

D11

FB_

OUT_

REF_

AGND

SHOWN FOR ALL 1s ON DAC

Figure 1. Simplified DAC Circuit Diagram

Output Amplifier

The output amplifier’s inverting input is available to the

user, allowing force and sense capability for remote

sensing and specific gain configurations. The inverting

input can be connected to the output to provide a unity-

gain buffered output. The output amplifiers have a typi-

cal slew rate of 0.75V/µs and settle to 1/2LSB within

15µs, with a load of 10kΩ in parallel to 100pF. Loads

less than 2kΩ degrade performance.

_______________________________________________________________________________________ 9

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