AD2S90 データシートの表示（PDF） - Analog Devices
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AD2S90 Datasheet PDF : 12 Pages
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AD2S90
TIMING CHARACTERISTICS1, 2 (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, TA = –40؇C to +85؇C unless
otherwise noted)
t2
t6
CSB
t3
SCLK
t4
t*
DATA
MSB
LSB
t1
t5
t7
*THE MINIMUM ACCESS TIME: USER DEPENDENT
Figure 1. Serial Interface
NOTES
1Timing data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 kΩ load.
2Capacitance of data pin in high impedance state = 15 pF.
Parameter
AD2S90
t1
150
t21
600
t3
250
t4
250
t5
100
t6
600
t7
150
NOTE
1SCLK can only be applied after t2 has elapsed.
Units
ns max
ns min
ns min
ns min
ns max
ns min
ns max
Test Conditions/Notes
CS to DATA Enable
CS to 1st SCLK Negative Edge
SCLK Low Pulse
SCLK High Pulse
SCLK Negative Edge to DATA Valid
CS High Pulsewidth
CS High to DATA High Z (Bus Relinquish)
A
B
90؇
NM 180؇
360؇
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
Figure 2. Incremental Encoder
Parameter
tDIR
tCLK
tABN
AD2S90
Min
Max
200
250
400
250
CLKOUT
A, B, NM
DIR
COUNTER IS CLOCKED
ON THIS EDGE
tCLK
tABN
tDIR
Figure 3. DIR/CLKOUT/A, B and NM Timing
Units
ns
ns
ns
Test Conditions/Notes
DIR to CLKOUT Positive Edge
CLKOUT Pulsewidth
CLKOUT Negative Edge to A, B and NM Transition
REV. D
–3–
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