MAX1710 データシートの表示（PDF） - Maxim Integrated

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MAX1710

High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs

Maxim Integrated 

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

fy factors that influence the turn-on and turn-off times.

These factors include the internal gate resistance, gate

charge, threshold voltage, source inductance, and PC

board layout characteristics. The following switching loss

calculation provides only a very rough estimate and is no

substitute for breadboard evaluation, preferably including

a sanity check using a thermocouple mounted on Q1:

()

PD(switching) = CRSS × VBATT(MAX)2 × f × ILOAD

IGATE

where CRSS is the reverse transfer capacitance of Q1

and IGATE is the peak gate-drive source/sink current (1A

typ).

For the low-side MOSFET, Q2, the worst-case power dis-

sipation always occurs at maximum battery voltage:

PD(Q2) = (1 - VOUT / VBATT(MAX)) ✕ ILOAD2 ✕ RDS(ON)

The absolute worst case for MOSFET power dissipation

occurs under heavy overloads that are greater than

ILOAD(MAX) but are not quite high enough to exceed the

current limit and cause the fault latch to trip. To protect

against this possibility, you must “overdesign” the circuit

to tolerate ILOAD = ILIMIT(HIGH) + (LIR / 2) ✕ ILOAD(MAX),

where ILIMIT(HIGH) is the maximum valley current allowed

by the current-limit circuit, including threshold tolerance

and on-resistance variation. This means that the

MOSFETs must be very well heatsinked. If short-circuit

protection without overload protection is enough, a nor-

mal ILOAD value can be used for calculating component

stresses.

Choose a Schottky diode D1 having a forward voltage

low enough to prevent the Q2 MOSFET body diode from

turning on during the dead time. As a general rule, a

diode having a DC current rating equal to 1/3 of the load

current is sufficient. This diode is optional, and if efficien-

cy isn’t critical it can be removed.

Application Issues

Dropout Performance

The output voltage adjust range for continuous-conduc-

tion operation is restricted by the nonadjustable 500ns

(max) minimum off-time one-shot. For best dropout per-

formance, use the slowest (200kHz) on-time setting.

When working with low input voltages, the duty-factor

limit must be calculated using worst-case values for on-

and off-times. Manufacturing tolerances and internal

propagation delays introduce an error to the TON K-fac-

tor. This error is higher at higher frequencies (Table 6).

Also, keep in mind that transient response performance

of buck regulators operated close to dropout is poor,

and bulk output capacitance must often be added (see

VSAG equation in the Design Procedure).

Dropout Design Example: VBATT = 3V min, VOUT =

2V, f = 300kHz. The required duty is (VOUT + VSW) /

(VBATT - VSW) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The

worst-case on-time is (VOUT + 0.075) / VBATT ✕ K =

2.075V / 3V ✕ 3.35µs-V ✕ 90% = 2.08µs. The IC duty-fac-

tor limitation is:

DUTY =

tON(MIN)

= 2.08µs + 500ns = 80.6%

tON(MIN) + tOFF(MAX)

which meets the required duty.

Remember to include inductor resistance and MOSFET

on-state voltage drops (VSW) when doing worst-case

dropout duty-factor calculations.

All-Ceramic-Capacitor Application

Ceramic capacitors have advantages and disadvan-

tages. They have ultra-low ESR, are noncombustible, are

relatively small, and are nonpolarized. On the other

hand, they’re expensive and brittle, and their ultra-low

ESR characteristic can result in excessively high ESR

zero frequencies (affecting stability). In addition, they

can cause output overshoot when going abruptly from

full-load to no-load conditions, unless there are some

bulk tantalum or electrolytic capacitors in parallel to

absorb the stored energy in the inductor. In some cases,

there may be no room for electrolytics, creating a need

for a DC-DC design that uses nothing but ceramics.

The all-ceramic-capacitor application of Figure 7 has the

same basic performance as the 7A Standard Application

Circuit, but replaces the tantalum output capacitors with

ceramics. This design relies on having a minimum of

5mΩ parasitic PC board trace resistance in series with

the capacitor in order to reduce the ESR zero frequency.

This small amount of resistance is easily obtained by

locating the MAX1710/MAX1711/MAX1712 circuit 2 or 3

inches away from the CPU, and placing all the ceramic

capacitors close to the CPU. Resistance values higher

than 5mΩ just improve the stability (which can be

observed by examining the load-transient response

characteristic as shown in the Typical Operating

Characteristics). Avoid adding excess PC board trace

resistance because there’s an efficiency penalty; 5mΩ is

sufficient for the 7A circuit.

Output overshoot determines the minimum output

capacitance requirement. In this example, the switching

frequency has been increased to 550kHz and the induc-

tor value has been reduced to 0.5µH (compared to

300kHz and 2µH for the standard 7A circuit) in order to

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